EDW2032BBBG-50-F-R TR

2Gb: x16, x32 GDDR5 SGRAM Features GDDR5 SGRAM EDW2032BBBG – 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks Features • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Address training: Address input monitoring via DQ pins • WCK2CK clock training: Phase information via EDC pins • Data read and write training via read FIFO (FIFO depth = 6) • Read FIFO pattern preloaded by LDFF command • Direct write data load to read FIFO by WRTR command • Consecutive read of read FIFO by RDTR command • Read/write data transmission integrity secured by cyclic redundancy check (CRC-8) • Read/write EDC on/off mode • Low power modes • RDQS mode on EDC pin • On-die temperature sensor with readout • Automatic temperature sensor controlled self refresh rate • Digital RAS lockout • Vendor ID, FIFO depth and density info fields for identification • Mirror function with MF pin • Boundary scan function with SEN pin VDD = V DDQ = 1.6V/1.5V ±3% and 1.35V ±3% Data rate: 5.0 Gb/s, 6.0 Gb/s, 7.0 Gb/s (MAX) 16 internal banks Four bank groups for tCCDL = 3 tCK 8n-bit prefetch architecture: 256-bit per array read or write access for x32; 128-bit for x16 Burst length (BL): 8 only Programmable CAS latency: 6–22 Programmable WRITE latency: 3–7 Programmable CRC READ latency: 1–3 Programmable CRC WRITE latency: 8–14 Programmable EDC hold pattern for CDR Precharge: Auto option for each burst access Auto refresh and self refresh modes Refresh cycles: 16,384 cycles/32ms Interface: Pseudo open drain (POD-15) compatible outputs: 40Ω pull-down, 60Ω pull-up On-die termination (ODT): 60Ω or 120Ω (NOM) ODT and output driver strength auto calibration with external resistor ZQ pin: 120Ω Programmable termination and driver strength offsets Selectable external or internal V REF for data inputs; programmable offsets for internal V REF Separate external V REF for address/command inputs TC = 0°C to +95°C x32/x16 mode configuration set at power-up with EDC pin Single-ended interface for data, address, and command Quarter data rate differential clock inputs CK_t, CK_c for address and commands Two half data rate differential clock inputs, WCK_t and WCK_c, each associated with two data bytes (DQ, DBI_n, EDC) DDR data (WCK) and addressing (CK) SDR command (CK) Write data mask function via address bus (single/ double byte mask) Data bus inversion (DBI) and address bus inversion (ABI) Input/output PLL on/off mode Duty cycle corrector (DCC) for data clock (WCK) PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN Options1 • Organization – Density – 64 Meg x 32 (words x bits) • FBGA package – 170-ball (12mm x 14mm) • Package environment code – Lead- and halogen-free (RoHS-compliant) • Package media – Dry pack (tray) – Reel • Timing – Cycle time – 5.0 Gb/s, 4.0 Gb/s – 6.0 Gb/s, 5.0 Gb/s – 7.0 Gb/s, 5.5 Gb/s • Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) • Revision Note: 1 Marking 20 32 BG -F -D -R -50 -6A -7A None B 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x16, x32 GDDR5 SGRAM Features Table 1: Addressing Parameter 128 Meg x 16 64 Meg x 32 Configuration 8 Meg x 16 x 16 banks 4 Meg x 32 x 16 banks Refresh count 16K/32ms 16K/32ms Refresh period 1.9µs 1.9µs Row addressing A[12:0] A[12:0] Bank addressing BA[3:0] BA[3:0] Column addressing A[6:0] A[5:0] Auto precharge A8 A8 Page size 2KB 2KB Figure 1: Part Numbering E D W 20 32 B B BG - 7A - F - D Elpida Memory Packing Media D = Dry pack (tray) R = Reel Type D = Packaged device Environment Code F = Lead-free (RoHS-compliant) and halogen-free Product Family W = GDDR5 SGRAM Speed -50 = 5.0 Gb/s -6A = 6.0 Gb/s -7A = 7.0 Gb/s Density/Bank 20 = 2Gb/16-bank Organization 32 = x32 Package BG = 170-ball FBGA, 12mm x 14mm Power Supply, Interface B = VDD = 1.6V/1.5V Revision FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site: http://www.micron.com. PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 2Gb: x16, x32 GDDR5 SGRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 2: 170-Ball FBGA – MF = 0 (Top View) 1 2 3 4 5 A VSSQ DQ1 VSSQ DQ0 B VDDQ DQ3 VDDQ C VSSQ EDC0 VSSQ D VDDQ DBI0_n VDDQ E VSSQ DQ5 VSSQ DQ4 F VDDQ DQ7 VDDQ G VDD VDDQ H VSS J 6 7 8 10 11 12 13 14 NC VREFD DQ8 VSSQ DQ9 VSSQ DQ2 VSS VSS DQ10 VDDQ DQ11 VDDQ VSSQ VDD VDD VSSQ VSSQ EDC1 VSSQ VSS VDD VDDQ DBI1_n VDDQ VDDQ VDDQ DQ12 VSSQ DQ13 VSSQ DQ6 VSSQ VSSQ DQ14 VDDQ DQ15 VDDQ RAS_n VDD VSS VSS VDD CS_n VDDQ VDD VSSQ VDDQ A10, A0 A9, A1 BA3, A3 BA0, A2 VDDQ VSSQ VSS MF RESET_n CKE_n ABI_n A12, RFU SEN CK_c CK_t ZQ VREFC K VSS VSSQ VDDQ A8, A7 A11, A6 BA1, A5 BA2, A4 VDDQ VSSQ VSS L VDD VDDQ CAS_n VDD VSS VSS VDD WE_n VDDQ VDD M VDDQ DQ31 VDDQ DQ30 VSSQ VSSQ DQ22 VDDQ DQ23 VDDQ N VSSQ DQ29 VSSQ DQ28 VDDQ VDDQ DQ20 VSSQ DQ21 VSSQ P VDDQ DBI3_n VDDQ VSS VDD VDDQ DBI2_n VDDQ R VSSQ EDC3 VSSQ VSSQ VDD VDD VSSQ VSSQ EDC2 VSSQ T VDDQ DQ27 VDDQ DQ26 VSS VSS DQ18 VDDQ DQ19 VDDQ U VSSQ DQ25 VSSQ DQ24 NC VREFD DQ16 VSSQ DQ17 VSSQ WCK01_t WCK01_c WCK23_t WCK23_c 9 (Top view) Data Note: PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN Addresses GDDR5 Supply Ground 1. Balls shown with a heavy, solid outline are off in x16 mode. 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 2Gb: x16, x32 GDDR5 SGRAM Ball Assignments and Descriptions Figure 3: 170-Ball FBGA – MF = 1 (Top View) 1 2 3 4 5 A VSSQ DQ25 VSSQ DQ24 B VDDQ DQ27 VDDQ C VSSQ EDC3 VSSQ D VDDQ DBI3_n VDDQ E VSSQ DQ29 VSSQ DQ28 F VDDQ DQ31 VDDQ G VDD VDDQ H VSS J 6 7 8 10 11 12 13 14 NC VREFD DQ16 VSSQ DQ17 VSSQ DQ26 VSS VSS DQ18 VDDQ DQ19 VDDQ VSSQ VDD VDD VSSQ VSSQ EDC2 VSSQ VSS VDD VDDQ DBI2_n VDDQ VDDQ VDDQ DQ20 VSSQ DQ21 VSSQ DQ30 VSSQ VSSQ DQ22 VDDQ DQ23 VDDQ CAS_n VDD VSS VSS VDD WE_n VDDQ VDD VSSQ VDDQ A8, A7 A11, A6 BA1, A5 BA2, A4 VDDQ VSSQ VSS MF RESET_n CKE_n ABI_n A12, RFU SEN CK_c CK_t ZQ VREFC K VSS VSSQ VDDQ A10, A0 A9, A1 BA3, A3 BA0, A2 VDDQ VSSQ VSS L VDD VDDQ RAS_n VDD VSS VSS VDD CS_n VDDQ VDD M VDDQ DQ7 VDDQ DQ6 VSSQ VSSQ DQ14 VDDQ DQ15 VDDQ N VSSQ DQ5 VSSQ DQ4 VDDQ VDDQ DQ12 VSSQ DQ13 VSSQ P VDDQ DBI0_n VDDQ VSS VDD VDDQ DBI1_n VDDQ R VSSQ EDC0 VSSQ VSSQ VDD VDD VSSQ VSSQ EDC1 VSSQ T VDDQ DQ3 VDDQ DQ2 VSS VSS DQ10 VDDQ DQ11 VDDQ U VSSQ DQ1 VSSQ DQ0 NC VREFD DQ8 VSSQ DQ9 VSSQ WCK23_t WCK23_c WCK01_t WCK01_c 9 (Top view) Data Note: PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN Addresses GDDR5 Supply Ground 1. Balls shown with a heavy, solid outline are off in x16 mode. 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 2Gb: x16, x32 GDDR5 SGRAM Ball Assignments and Descriptions Table 2: 170-Ball FBGA Ball Descriptions Symbol Type Description A[12:0] Input Address inputs: Provide the row address for ACTIVE commands. A[5:0] (A6) provide the column address and A8 defines the auto precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA[3:0]) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command and the data bits during LDFF commands. A[12:8] are sampled with the rising edge of CK_t and A[7:0] are sampled with the rising edge of CK_c. ABI_n Input Address bus inversion: Reduces the power requirements on address pins by limiting the number of address lines driving LOW to 5. ABI_n is enabled by the corresponding ABI mode register bit. BA[3:0] Input Bank address inputs: Define the bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[3:0] define which mode register is loaded during the MODE REGISTER SET command. BA[3:0] are sampled with the rising edge of CK_t. CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on the rising edge of CK_t. Address inputs are latched on the rising edge of CK_t and the rising edge of CK_c. All latencies are referenced to CK_t. CK_t and CK_c are externally terminated. WCK01_t, WCK01_c/ WCK23_t, WCK23_c Input Data Clocks: WCK_t and WCK_c are differential clocks used for write data capture and read data output. WCK01_t and WCK01_c are associated with DQ[15:0], DBI0_n, DBI1_n, EDC0, and EDC1. WCK23_t and WCK23_c are associated with DQ[31:16], DBI2_n, DBI3_n, EDC2, and EDC3. WCK clocks operate at nominally twice the CK clock frequency. CKE_n Input Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) internal circuitry and clocks on the SGRAM. The specific circuitry that is enabled/disabled is dependent upon the device configuration and operating mode. Taking CKE_n HIGH provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE_n is synchronous for power-down entry and exit and for self refresh entry. CKE_n must be maintained LOW throughout read and write accesses. Input buffers (excluding CKE_n) are disabled during SELF REFRESH operation. The value of CKE_n latched at power-up with RESET_n going HIGH determines the termination value of the address and command inputs. CS_n Input Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS_n is registered HIGH, but internal command execution continues. CS_n is considered part of the command code. MF Input Mirror function: VDDQ CMOS input. Must be tied to VDDQ or VSS. RAS_n, CAS_n, WE_n Input Command inputs: RAS_n, CAS_n, and WE_n (along with CS_n) define the command being entered. RESET_n Input Reset: RESET_n is an active LOW CMOS input referenced to VSS. A full chip reset may be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are disabled. SEN Input Scan enable: VDDQ CMOS input. Must be tied to VSS when not in use. PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 2Gb: x16, x32 GDDR5 SGRAM Ball Assignments and Descriptions Table 2: 170-Ball FBGA Ball Descriptions (Continued) Symbol Type DQ[31:0] I/O Data input/output: Bidirectional 32-bit data bus. Description DBI[3:0]_n I/O Data bus inversion: Reduces the DC power consumption and supply noise induced jitter on data pins. DBI0_n is associated with DQ[7:0], DBI1_n with DQ[15:8], DBI2_n with DQ[23:16], and DBI3_n with DQ[31:24]. EDC[3:0] Output Error detection code: The calculated CRC data is transmitted on these pins. In addition, these pins drive a hold pattern when idle and can be used as an RDQS function. EDC0 is associated with DQ[7:0], EDC1 with DQ[15:8], EDC2 with DQ[23:16], and EDC3 with DQ[31:24]. VDD Supply Power supply: 1.6V/1.5V ±3% and 1.35V ±3%. VDDQ Supply DQ power supply: 1.6V/1.5V ±3% and 1.35V ±3%. Isolated on the device for improved noise immunity. VREFC Supply Reference voltage for control and address: VREFC must be maintained at all times (including self refresh) for proper device operation. VREFD Supply Reference voltage for data: VREFD must be maintained at all times (including self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC – PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN External reference ball for output drive calibration: This ball is tied to an external 120Ω resistor (ZQ), which is tied to VSSQ. No connect: These balls should be left unconnected (the ball has no connection to the SGRAM or to other balls). 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 2Gb: x16, x32 GDDR5 SGRAM Package Dimensions Package Dimensions Figure 4: 170-Ball FBGA (BG) 0.2 0.35 ±0.05 S 1.1 ±0.1 S 0.12 S 170- 0.45 ±0.05 12.0 ±0.1 Ball A1 ID A 0.2 S A Ball A1 ID 0.15 M S A B A B C D E F G H J K L M N P R T U 0.8 B 12.8 14.0 ± 0.1 2.0 0.2 0.8 S B 10.4 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef858b7e99 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.